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| TSH321 WIDE BANDWIDTH AND MOS INPUT SINGLE OPERATIONAL AMPLIFIER s s s s s s LOW DISTORTION GAIN BANDWIDTH PRODUCT : 300MHz GAIN OF 2 STABILITY SLEW RATE : 400V/s VERY FAST SETTLING TIME : 60ns (0.1%) VERY HIGH INPUT IMPEDANCE DESCRIPTION The TSH321 is a wideband monolithic operational amplifier, requiring a minimum close loop gain of 2 for stability. The TSH321 features extremely high input impedance (typically greater than 1012) allowing direct interfacing with high impedance sources. Low distortion, wide bandwidth and high linearity make this amplifier suitable for RF and video applications. Short circuit protection is provided by an internal current-limiting circuit. The TSH321 has internal electrostatic discharge (ESD) protection circuits and fulfills MILSTD883C-Class2. ORDER CODE Package Part Number TSH321I Temperature Range D -40C, +125C * D SO8 (Plastic Micropackage) PIN CONNECTIONS (top view) Offset Null 1 Inverting Input Non-inverting Input V CC 1 2 3 4 8 Offset Null 2 7 VCC+ 6 5 Output N.C. D = Small Outline Package (SO) - also available in Tape & Reel (DT) October 2000 1/5 TSH321 SCHEMATIC DIAGRAM 7 VCC + non inverting input 3 Internal Vref 6 output 2 inverting input 1 Offset N1 8 Cc Offset N2 4 VCC- INPUT OFFSET VOLTAGE NULL CIRCUIT TSH321 N1 N2 100k V CC MAXIMUM RATINGS Symbol VCC Vid Vi Iin Toper Supply Voltage Differential Input Voltage Input Voltage Current On Offset Null Pins Operating Free-Air Temperature range Parameter Value 7 5 5 20 -40 to +125 Unit V V V V C OPERATING CONDITIONS Symbol VCC Vic Supply Voltage Common Mode Input Voltage Range Parameter Value 3 to 6 VCC to VCC -3 + Unit V V 2/5 TSH321 ELECTRICAL CHARACTERISTICS VCC = 5V, Tamb = 25C (unless otherwise specified) Symbol Vio DVio Iib Iio Parameter Input Offset Voltage Tmin. Tamb Tmax Input Offset Voltage Drift Tmin. Tamb Tmax. Input Bias Current. Input Offset Current. Supply Current, no load ICC Tmin. Tamb Tmax Avd Vicm CMR SVR VCC = VCC = VCC = VCC = 5V 3V 6V 5V 800 300 200 -5 to +2 60 50 3 2.8 2.9 2.7 50 100 300 200 400 mA MHz V/s 23 21 25 30 28 40 32 mA Min. Typ. 0.5 Max. 10 12 Unit mV V/C 300 200 pA pA 10 2 2 Large Signal Voltage Gain Vo = 2.5V RL = RL = 100 RL = 50 Input Common Mode Voltage Range Common-mode Rejection Ratio Vic = Vicm min. Supply Voltage Rejection Ratio VCC = 5V to 3V Output Voltage RL = 100 1300 850 650 -5.5 to +2.5 100 70 +3.5 -3.7 +3.3 -3.5 V/V V dB dB Vo Tmin. Tamb Tmax Io GBP SR RL = 50 RL = 100 RL = 50 V Output Short Circuit Current Vid = 1V, Vo = 0V Gain Bandwidth Product AVCL = 100, RL = 100, CL = 15pF, f = 7.5MHz Slew Rate Vin = 1V, AVCL = 2, RL = 100, CL = 15pF Equivalent Input Voltage Noise Rs = 50 en fo = 1kHz fo = 1k0Hz fo = 100kHz fo = 1MHz Overshoot Vin = 1V, AVCL = 2, RL = 100, CL = 15pF Settling Time 0.1% Vin = 1V, AVCL = -1 Rise and Fall Time (see note 1) Vin = 100mV, AVCL = 2 Delay Time (see note 1) Vin = 100mV, AVCL = 2 Phase Margin AVM = 2, RL = 100, CL = 15pF Total Harmonic Distortion AVCL = 10, f = 1kHz, Vo = 2.5V, no load Full Power Bandwidth 2) Vo = 5Vpp, RL = 100 Vo = 2Vpp, RL = 100 SR ------------------ Vopp 1) 20 18.2 18.1 18.2 15 60 2 2 45 0.02 26 64 nV/Hz Kov ts tr, tf td m THD % ns ns ns Degrees % FPB MHz 1. See test waveform figure 2. Full power bandwidth = 3/5 TSH321 TEST WAVEFORM EVALUATION CIRCUIT +5V 10F 50 10nF Input ts 0.1% of edge amplitude 50 Output 1k 10nF 90% td 50% tr Vin 10% -5V 10F 1k CF PRINTED CIRCUIT LAYOUT As for any high frequency device, a few rules must be observed when designing the PCB to get the best performances from this high speed op amp. From the most to the least important points : order to decrease parasitic capacitance and inductance. u Use small resistor values to decrease time constant with parasitic capacitance. u Each power supply lead has to be bypassed to ground with a 10nF ceramic capacitor very close to the device and a 10F tantalum capacitor. u To provide low inductance and low resistance common return, use a ground plane or common point return for power and signal. u All leads must be wide and as short as possible especially for op amp inputs. This is in u Choose component sizes as small as possible (SMD). u On output, decrease capacitor load so as to avoid circuit stability being degraded which may cause oscillation. You can also add a serial resistor in order to minimise its influence. u One can add in parallel with feedback resistor a few pF ceramic capacitor CF adjusted to optimize the settling time. 4/5 TSH321 PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 1.27 0.6 8 (max.) 0.150 0.016 Typ. Max. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 5.0 6.2 0.189 0.228 Min. 0.004 0.026 0.014 0.007 0.010 Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 5/5 |
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